//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
// Example External Special Function Registers for M8051W/EW soft core
// 
// $Log: esfr.v,v $
// Revision 1.12  2001/11/20
// First checkin of version 2 features and name change
//
// Revision 1.1  2001/11/14
// First EW checkin
//
// Revision 1.11  2001/07/10
// Tidy up
//
// Revision 1.10  2000/03/06
// Revised configuration scheme
//
// Revision 1.9  2000/02/23
// First code freeze
//
// Revision 1.8  2000/02/15
// Renamed extra interrupts as extended interrupts
//
// Revision 1.7  2000/02/05
// Name change from m8051e to m8051ewarp
//
// Revision 1.6  2000/02/03
// *** empty log message ***
//
// Revision 1.5  2000/02/01
// Configuration status calculated automatically
//
// Revision 1.4  2000/02/01
// Added configuration status ESFR to test bench
//
// Revision 1.3  2000/01/05
// Test bench updates, wait generator moved to separate module.
//
// Revision 1.2  1999/11/19
// SFR read enable modelling added, corrections to debug testing.
//
// Revision 1.1.1.1  1999/10/28
// "initialization and source check-in for m8051e"
//
//
////////////////////////////////////////////////////////////////////////////////
//
// Purpose      :       Example of two external peripheral SFRs for the
//              :       M8051W/EW Soft Core.
//              :       These registers also provide a source for extended
//              :       interrupts 6 to 14 and the non-maskable interrupt.
//
////////////////////////////////////////////////////////////////////////////////

`include "m8051w_cfg.v"
`include "m8051w_tb_cfg.v"

module esfr (ESFRDI, XINTR_SRC, NMI, SFRSA, DESTIN_A, SFRWE, SFRRE, DESTIN_DO,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
             XINTR_ACK, NMI_ACK, CLK, RESET);

  output [7:0]  ESFRDI;
  output [13:0] XINTR_SRC;
  output        NMI;

  input  [6:0]  SFRSA;
  input  [7:0]  DESTIN_A, DESTIN_DO;
  input  [13:0] XINTR_ACK;
  input         NMI_ACK;
  input         SFRWE, SFRRE, RESET, CLK;

  reg    [7:0]  ESFR_0, ESFR_1;          // two ESFRs for extended interrupts
  reg    [7:0]  ESFRDI;
  wire   [7:0]  CFG_Status1;             // read only core configuration	
  wire   [7:0]  CFG_Status2;             // read only core configuration	

  // Set up the configuration word

  `ifdef ExcludeUART
    assign CFG_Status1[0] = 1'b1;
  `else
    assign CFG_Status1[0] = 1'b0;
  `endif
  `ifdef ExcludeTimers
    assign CFG_Status1[1] = 1'b1;
  `else
    assign CFG_Status1[1] = 1'b0;
  `endif
  `ifdef ExcludePorts
    assign CFG_Status1[2] = 1'b1;
  `else
    assign CFG_Status1[2] = 1'b0;
  `endif
  `ifdef MappedDataPointers
    assign CFG_Status1[3] = 1'b1;
  `else
    assign CFG_Status1[3] = 1'b0;
  `endif
  `ifdef BankedDataPointers
     assign CFG_Status1[5:4] = `BankedDataPointers;	
  `else
    assign CFG_Status1[5:4] = 2'b00;
  `endif
  `ifdef ExtraInterrupts
    assign CFG_Status1[6] = 1'b1;
  `else
    assign CFG_Status1[6] = 1'b0;
  `endif
  `ifdef ExtraPriorities
    assign CFG_Status1[7] = 1'b1;
  `else
    assign CFG_Status1[7] = 1'b0;
  `endif
  `ifdef ExcludeTimer2
    assign CFG_Status2[0] = 1'b1;
  `else
    assign CFG_Status2[0] = 1'b0;
  `endif
  `ifdef MemExtend
    assign CFG_Status2[1] = 1'b1;
  `else
    assign CFG_Status2[1] = 1'b0;
  `endif
  assign CFG_Status2[7:2] = 6'b000000;

  // Model of a pair of writable external SFR registers.

  always @(posedge CLK or RESET) begin

    if (RESET) begin
      ESFR_0 <= 8'h00;
      ESFR_1 <= 8'h00;
    end
    else if (|XINTR_ACK[13:5] || NMI_ACK) begin
      ESFR_0[7:0] <= ESFR_0[7:0] & ~XINTR_ACK[12:5];
      ESFR_1[0]   <= ESFR_1[0] & ~XINTR_ACK[13];
      ESFR_1[7]   <= ESFR_1[7] & ~NMI_ACK;
    end
    else if (SFRWE)
        case(DESTIN_A)
          `Addr_ESFR0: ESFR_0 <= DESTIN_DO;
          `Addr_ESFR1: ESFR_1 <= DESTIN_DO;
        endcase
  end

  // External SFR data multiplexer - bus holder is 00h.
  // This multiplexer uses a case equality test on SFRRE to block X propagation
  // during simulator initialisation.
  always @(SFRSA or SFRRE or ESFR_0 or ESFR_1 or CFG_Status1 or CFG_Status2)
  begin: ESFR_mux
    if (SFRRE === 1'b1)
      ESFRDI <= ({8{({1'b1,SFRSA} == `Addr_ESFR0) }} & ESFR_0) |
                  ({8{({1'b1,SFRSA} == `Addr_ESFR1) }} & ESFR_1) |
                  ({8{({1'b1,SFRSA} == `Addr_CFG1) }} & CFG_Status1) |
                  ({8{({1'b1,SFRSA} == `Addr_CFG2) }} & CFG_Status2);
    else
      ESFRDI <= 8'h00;

  end

  // Connect extended interrupt sources to ESFR register bits
  assign XINTR_SRC[13:0] = {ESFR_1[0], ESFR_0[7:0], 5'b00000};
  assign NMI = ESFR_1[7];

endmodule
